A boost power-factor-correction stage asks one magnetic component to operate across the AC line cycle, input-voltage range, load range, and switching pattern. The boost PFC inductor design must retain adequate inductance under peak current, limit ripple, avoid core saturation, control copper and core loss, meet EMI objectives, and remain within temperature limits. Continuous-conduction mode (CCM) and boundary-conduction mode (BCM or CrM) place notably different demands on that component.
Current waveform across the line cycle
For a well-controlled PFC stage, average input current follows the rectified line voltage. Switching ripple rides on that envelope. Near the line-voltage zero crossing, duty cycle and current-sense limitations can distort current. Near the line peak, the available boost voltage across the inductor changes. The magnetic design should use time-domain current and voltage waveforms rather than one RMS number.
Low-line, full-load operation often produces the highest RMS and peak current. High line may produce a different worst case for duty-dependent ripple or core loss. Brownout recovery, startup, output short circuit, and control saturation can expose the inductor to transient volt-seconds that do not occur in steady-state calculations.
CCM design priorities
In CCM, current does not normally fall to zero during a switching period. Inductance is selected to keep peak-to-peak ripple within a target over line and load. Higher inductance reduces ripple and may ease differential-mode EMI, but generally requires more turns, a larger core, or a smaller effective gap. More turns increase DC resistance and can increase AC proximity loss.
The core stores substantial energy under DC bias. Powder cores with distributed gap or gapped ferrite structures are common choices. A discrete ferrite gap can support low core loss, but fringing field near the gap can cause severe localized winding loss if copper is placed too close. Distributed-gap materials reduce localized fringing but have their own loss, permeability, and cost tradeoffs.
Boundary-mode design priorities
In boundary mode, each switching cycle begins when inductor current returns to approximately zero. Switching frequency varies with instantaneous line voltage and load. Peak current is higher than in a comparable low-ripple CCM stage, and the component repeatedly traverses a larger AC flux excursion.
Zero-current turn-on can reduce diode reverse-recovery stress, but variable frequency spreads the loss and EMI problem across a wide band. At light load, valley switching, frequency clamp, or burst operation changes the waveform again. Core-loss estimation must cover the actual frequency-flux trajectory rather than a single rated frequency.
Inductance under bias and tolerance
The useful specification is inductance at defined current and temperature. Initial inductance at a small test signal is not enough. Permeability falls with DC bias in powder materials, while a gapped ferrite design may hold inductance more consistently until it approaches saturation. Gap tolerance, core tolerance, turns count, assembly pressure, and temperature all contribute to production spread.
Minimum inductance determines maximum ripple and peak current. Maximum inductance can affect transient response, BCM timing, and control limits. BaoHui Tech therefore recommends specifying both a zero-bias window and a minimum value at the relevant peak or average current.
Copper loss at switching frequency
DC resistance is only one part of winding loss. Skin effect increases conductor resistance with frequency, and proximity effect redistributes current in the magnetic field created by neighboring turns and gap fringing. Round wire, parallel strands, litz wire, foil, edge-wound copper, or flat wire can each be appropriate depending on current, frequency, window, cost, and cooling.
Litz wire is not automatically the best option. Strand diameter, strand count, bunching, termination, fill factor, and frequency spectrum determine its benefit. Poorly terminated litz can add resistance and manufacturing variation that offsets the theoretical AC-loss advantage.
EMI and parasitic capacitance
Inductor parasitic capacitance creates a self-resonance and can reduce high-frequency impedance. Winding layers, start-finish separation, core proximity, and electrostatic environment influence this capacitance. The PFC switching node also drives common-mode current through parasitic capacitances to chassis and heatsinks, so the boost inductor cannot be optimized only for differential ripple.
Validation checklist
- Measure inductance at zero bias and under DC current across temperature.
- Capture current and winding voltage across the full rectified line cycle.
- Check peak current during startup, brownout recovery, overload, and mode changes.
- Measure winding and core temperatures at low and high line in the final airflow.
- Verify conducted emissions with production-equivalent winding and layout.
- Confirm acoustic behavior during burst, frequency clamp, and light-load operation.
Frequently asked questions
Is the highest PFC inductor current always at low line?
Low line usually gives the highest input current at a given power, but transient control behavior, ripple, duty cycle, and thermal conditions should be checked before declaring the single worst case.
Why can a gapped ferrite inductor overheat near the gap?
Fringing flux crosses nearby conductors and induces eddy currents. Winding placement, gap distribution, conductor geometry, and shielding determine the local loss.
What does BaoHui Tech need for a custom PFC inductor?
Provide topology and control mode, line and output ranges, power, switching-frequency behavior, current and voltage waveforms, ripple target, transient limits, cooling, size, insulation, EMI constraints, and annual volume.